Samsung Electronics plans to use Taiwan Semiconductor Manufacturing Co.’s 3-nanometer manufacturing process for base dies in Nvidia’s next-generation custom high-bandwidth memory chips, according to an October 18 report by the Seoul Economic Daily.
The report follows a sharp increase in TSMC’s quarterly earnings. In its October 15 results releasethe company reported third-quarter net income of NT$763.06 billion, up 68.7% from a year earlier. Revenue reached NT$1,494.24 billion, an increase of 50.9%. Diluted earnings were NT$29.43 per share, equivalent to US$4.60 per ADR unit.
Measured in U.S. dollars, revenue was $46.72 billion, up 41.2% year over year. TSMC said its 3-nanometer process accounted for 33% of wafer revenue during the quarter ended September 30. Its newer 2-nanometer technology contributed 8%.
Chief Financial Officer Wendell Huang attributed quarterly performance to strong demand for leading-edge processes. For the fourth quarter, management forecast revenue of $52.3 billion to $54.3 billion. That outlook accompanied the earnings announcement and predates Sunday’s report about Samsung.
The memory industry is also preparing for a larger allocation of production capacity to HBM. On September 29, Samsung Executive Vice President Kim Taewoo said HBM was expected to consume nearly 30% of DRAM producers’ wafer capacity in 2027, compared with about 20% currently, Reuters reported.
Kim said HBM and conventional DRAM compete for the same wafer capacity, so expanding HBM production could constrain standard DRAM supply. HBM uses vertically stacked memory chips to give processors rapid access to large amounts of data for artificial intelligence computing.
Source: finchannel.com
